1/9 L6670 may 2000 this is preliminary information on a new product now in development. details are subject to change without notice. n high sensitivity n 7 bit a/d converter (+ 1 sign bit) n 800hz bandwidth n 300 rad/sec 2 full scale value n digital decimator filter n serial port output description the L6670 is a complete rotational accelerometer system based on a s - d architecture, followed by a digital decimator filter, featuring high sensitivity, 800hz signal bandwidth and a complete serial port interface for a direct connection to microprocessor environment. package ordering number: L6670 product preview angular accelerometer block diagram a/d converter sensor digital filter ser. ifc spe d00in1117 spd spc
L6670 2/9 pin function pin connections (top view) n. pin name function typ. condition 1 to 6 nc not connected 7 vdd_analog analog voltage supply 5v typ. 8 ref_cap reference voltage bypass 9 hv_eprom eprom programming voltage (test mode only) tied to gnd 10 vdd_digital digital voltage supply 5v typ. 11 spc serial port clock signal 12 spd serial port data signal 19 to 24 nc not connected 13 spe serial port enable signal 14 clk_in external clock input 15 gnd_digital digital ground pin 16 test_funct self test 17 test_st test pin tied to gnd 18 gnd_analog analog ground pin n.c. n.c. n.c. n.c. n.c. v dd _analog n.c. ref_cap hv_eprom test_funct test_st gnd_analog n.c. n.c. n.c. n.c. n.c. n.c. 1 3 2 4 5 6 7 8 9 22 21 20 19 18 16 17 15 23 10 24 v dd _digital gnd_digital d00in1116 spc clk_in 11 14 13 12 spd spe
3/9 L6670 absolute maximum ratings electrical characteristcs symbol parameter value unit vdd analog max maximum analog supply voltage 7 v vdd digital max maximum digital supply voltage 7 v v in voltage range on spc, spe, spd, clk_in, test_funct -0.3 to vdd dig + 0.3 symbol parameter test condition min. typ. max. unit dc vdd analog analog supply voltage 4.5 5.0 5.5 v vdd digital digital supply voltage 4.5 5.0 5.5 v idd analog analog circuitry supply current 10 ma idd digital digital circuitry supply current 10 ma v ref voltage on ref_cap pin 2.285 v v oh (on spd and test_funct) @ i oh =5ma >4.0 v v ol (on spd and test_funct) @ i ofl = 5ma <1.0 v v ih (on spc, spd, spe, clk_in and test_funct) tbd v v il (on spc, spd, spe, clk_in and test_funct) tbd v adc adc snr (30-800hz, 4.48mhz ext.clk) 40 db adc full scale 300 rad/ sec2 adc bandwidth 30-800 hz adc dynamic range 40 db adc differential linearity tbd adc integral linearity <5% full scale mclk clock frequency on clk_in pin 6 mhz
L6670 4/9 serial port timings figure 1. application diagram symbol parameter test condition min. typ. max. unit pin spc fpc spc frequency mclk 11 mhz pin spe tec spe to spec 30 45 ns tce spc to spe 30 45 ns twe spe low 1 spc period pin spd (input) tds spd to spc 10 ns tdh spc to spd 5 ns pin spd (output) tpd spc to spd 40ns (c l = 20pf) 18 7 8 10 17 16 15 14 13 spe spd spc d00in1118 serial i/o external clk 12 11 c1 22 m f 6v v cc gnd c2 0.22 m f c3 220pf c4 0.22 m f c5 0.22 m f 9
5/9 L6670 serial port, registers, eprom and test modes 1. serial port 1.1 read & write register figure 2. spe is the serial port enable. it goes high at the start of the transmission and goes back low at the end. spc is the serial port clock. it is stopped high when spe is low (no transmission). spd is the serial port data. it is driven by the falling edge of spc. it should be captured at the rising edge of spc. the read register or write register command consists of 16 clocks or bits. a bit duration is the time between two falling edges of spc. the first bit (bit 0) starts at the first falling edge of spc after the rising edge of spe and the last bit (bit 15) starts at the last falling edge of spc just before the falling edge of spe. n bit 0 : rw bit. when 0, the data (d7:0) is written into the mu05. when 1, the data (d7:0) from the mu05 is read. in this case, the mu05 will drive spd at the start of bit 8. n bit 1-3 : chip id. the chip id for the mu05 is id(2:0)=110. the mu05 accepts the command only when the id is valid (equal to 110). n bit 4-7 : address ad(3:0). this is the address field for the registers. see section 2 for more details. n bit 8-15 : data d(7:0). this is the data that will be written (read) into (from) the register which address is ad(3:0). 1.2 read fifo figure 3. spe spc spd rw id2 id1 id0 ad3 ad2 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 d00in1119 spe spc spd rw id2 id1 id0 ad3 ad2 ad1 ad0 d7-0 d6-0 ..... d0-0 d7-1 d6-1 ..... d0-1 d00in1120
L6670 6/9 the read fifo command consists of 24 clocks or bits. bit0:readbit.thevalueis1. bit 1-3 : chip id. id(2:0)=110. bit 4-7 : fifo address. the fifo has four registers grouped into two banks. the first bank consists of the first and the second register. the first register is the one written first since the last read. the second bank consists of the third and fourth register. 000x: address for the first bank 001x: address for the second bank bit 8-23: fifo data. the mu05 puts out first the data of the first register of the bank with the msb first. 2. mu05 registers the following is the address ad(3:0) of the registers. ad(3:0) = 0100 ctrl_reg this is the control register. it has 8 bits. the following gives the description of the bits. note: x means don't care value. note: default value after power on reset is 0000 0000. xxx1 xxxx: set to internal clock. by default the clock is external via pin varie. xx1x xxxx: low power mode for the eprom. 1xxx xxxx: clip on. the result of the multiplier is clipped to 0111 1111 when greater than 127 or 1000 0000 when less than -128. xxxx 0001: bitstream in mode. the bitstream is sent in via pin test_funct while ck1m6 (bitstream clock) is sent in via pin varie and the output can be checked via the serial interface. xxxx 0010: bitstream out mode. the bitstream is sent out to the pin spc while ck1m6 is sent out to the pin spe and phase_16 (digital filter clock) is sent out to the pin spd. the pin test_st must be set to 9 volts. xxxx 0100: eprom write. writing to a register (see below) also addresses the eprom and with the pin hv_eprom = 15 volts, moving the pin test_funct to 5 volts the eprom is written with the same contents as with the register. xxxx 0101: eprom read. sending a read register command reads the eprom instead of the register. xxxx 0110: sensor offset actuation. xxxx 0111: sensor offset trim. xxxx 1000: common mode feed-back trim. ad(3:0)= 1000 gain_lsb this is the 8 lsb of the gain for the digital filter. ad(3:0)= 1001 gain_msb this is the 8 msb of the gain for the digital filter. ad(3:0)= 1010 offs_lsb this is the 8 lsb of the offset for the digital filter.
7/9 L6670 ad(3:0)= 1011 offs_msb this is the 8 msb of the offset for the digital filter. ad(3:0)= 1100 cfb_trim this is the 8 bits for the common mode feedback trim. ad(3:0)= 1101 cs_act this is the 8 bits for the sensor offset actuation. ad(3:0)= 1110 cs_trim this is the 8 bits for the sensor offset trim. ad(3:0)= 1111 eprom_test this is the 8 bits used to store the value of the eprom threshold voltage.
L6670 8/9 so24 dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 a2 2.55 0.100 b 0.33 0.51 0.013 0.0200 c 0.23 0.32 0.009 0.013 d 15.20 15.60 0.598 0.614 e 7.40 7.60 0.291 0.299 e 1.27 0,050 h 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 k0 (min.), 8 (max.) l 0.40 1.27 0.016 0.050 be a2 a 1 13 24 d l h a1 c e k h x 45? so24 seating plane 0.10mm .004 a1 outline and mechanical data 12
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